The economics of the chip industry are pretty staggering. Sanjay Jha, CEO of contract chip manufacturer Globalfoundries, recently told me that it could cost $10 billion to $12 billion to build a next-generation chip factory, based on the latest technology dubbed 7-nanometer production. And the generation after that, dubbed 5-nanometer production, could cost $14 billion to $18 billion.
There are only a few companies in the world that can afford to spend that much money on a chip factory. And they can do it because those chips are expected to generate billions of dollars in revenue over the life of the factories.
Intel, the world’s biggest chip maker, can certainly afford that. Globalfoundries is one of the companies that enables all of the other chip design companies to keep up. Globalfoundries’ customers, such as Advanced Micro Devices, design the chips such as Ryzen desktop processors that power the modern electronics world. And Globalfoundries handles the gargantuan technical task of building the factories that fabricate those chips with precision equipment. As a foundry, the company offloads the manufacturing so that its customers can focus on design.
As a contract manufacturer, Globalfoundries creates opportunities for companies that want to provide alternatives to Intel and others in the chip business. Globalfoundries was once part of AMD. It recapitalized and spun out of AMD as an independent contract manufacturer in 2009, and it acquired both Chartered Semiconductor and IBM Microelectronics. Globalfoundries still has a tight relationship with AMD as a maker of chips based on AMD’s chip designs. It is owned by the Mubadala Investment Company. I spoke with Jha about the state of the global chip manufacturing business.
Here’s an edited transcript of our interview.
Sanjay Jha: The newsworthy part, mildly news, is we’re announcing the 12nm FinFET technology. As you know, all AMD products – Radeon, Ryzen, Epyc – have been done by us. They want a faster process, a little scaling of the process. To compete with Nvidia using 12nm from TSMC, we’re offering them a 12nm process to continue to deliver faster clock speeds and performance.
VB: Where is that at this point?
Jha: I don’t know when they’ll have products for us, but they’re designing to it already. Our factories are ready to deliver those things.
VB: The discussion I always get it into at this point is nobody agrees what really is 12nm or 10nm and who’s really ahead.
Jha: I’ll step into that discussion. Basically, the numbers don’t mean much these days. I think Samsung has talked about 10nm, 11nm, 14nm, 8nm, 7nm, 6nm. I don’t know what they mean. The way to think about 12nm is it has higher performance and more scale than 14nm. It’s not quite the scaling or performance of 10nm. Performance may be very close to 10nm, though.
What has happened, as the line widths get closer, it’s getting harder and harder to get incremental performance. You can get scale that you want, but getting performance is harder. You can get some power consumption reduction as well. With 14nm most people use .8. At 10nm most people are using .7. As you go there’s a clear scaling with the ratio of the squares of those two numbers. That gives you about 20-25 percent reduction in power consumption. So we deliver performance, some power consumption reduction, and scaling.
Exactly what they mean, though—if you go from 7nm to 5nm, looking at the square of the two numbers, the ratio is close to half. That’s long since gone. What you’re seeing more nowadays is people optimizing their technology for particular applications. We have a technology called 12 FDSOI. That turns out to be a very interesting technology because, first of all, it’s a planar transistor, not a FinFET transistor. Therefore the complexity of the process lower. It tends to have lower leakage current. Because it has higher performance, it tends to have lower dynamic power for any performance. What you do, to get any performance, you scale your voltage down a bit and get the power savings. 12 FDSOI is very interesting and it’s getting a lot of traction.
One other reason why it’s getting traction is because FDSOI turns out to be very good for integration with analog and RF. As you know, more of the edge devices are now wirelessly connected than ever before. You have Bluetooth or wi-fi or full WAN radio integrated. If you want to do that, FDSOI turns out to be a very good technology. That’s part of the reason why we conceived of the FDSOI series – battery-powered, connected, cost-sensitive devices.
IOT falls in that category. Automotive falls in that category. Increasingly I think you’ll see 5G fall in that category. At the same time, one reason we went from 22nm to 12nm—because of edge AI you need more transistors and more circuit. We scaled the technology to deliver more real time edge decision-making in 12nm.
VB: As far as how quickly the manufacturing could scale up, when you have these new AMD parts coming in—their financials didn’t seem to reflect what you would think would happen when you have a superior product on the market. It seemed very gradual to me. It seemed like multiple quarters might be the time frame.
Jha: Certainly two or three quarters. That’s generally the case in semiconductor. The only place where you see incredible ramps these days is in mobile. The volume is so large that people dedicate whole fabs to ramp the technology. In the old days ramps always happened slowly. There’s a very big Christmas effect in mobile. You announce a part in August-September, launch a product in late September, and have a quarter worth of shipping products for the Christmas season. Mobile has been unique in that.
VB: It’s possible that someone could introduce something and you might not see big effects until a year later?
Jha: A year later would be long. But remember, in mobile—particularly Apple controls the hardware, software, and apps ecosystem. In PC, generally you have to think about when the chips become available, when the APIs become available, when the games become available, when the games become optimized. In PCs, the dads and grads and back to school are the two big seasons. There’s a little Christmas effect as well, a little more diffuse than in mobile. In mobile the fourth quarter is always the big one. But there are different dynamics as to how quickly things ramp.
VB: For you guys, it’s not necessarily learning how to do this. It’s more how the demand comes in?
Jha: Right. We’re in full ramp. There’s a bit of learning in every part you do. There’s a little learning from our point of view to understand what the yield sensitivities are from AMD’s point of view, and understanding if they’ve debugged every last thing. There are often minor ramps of parts, either for optimization, power reduction, or bug fixes. That happens, and it does play a role in the ramp. But not a big one. Occasionally you see those things.
VB: Going back to where the specs are on nanometers, how do customers view the problem of figuring out who’s really ahead of the game as far as manufacturing?
Jha: They look at four things. They look at density, performance, power consumption, and cost. We call it PPAC. That’s what most customers care about. They don’t care about 12nm or 10nm. Even if the density of 12nm is a little lower than 10nm, if the complexity of the process is lower and the cost is lower and the power consumption may be lower, that may allow them to go after the mobile space a little better than 10nm. They look at the PPAC and target it to particular models.